1. Field of Invention
Embodiments of the present invention generally relate to semiconductor devices and methods of fabricating the same and, more particularly, to a semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same.
2. Description of Related Art
Owing to the increased demand for highly integrated semiconductor devices, laborious research has been conducted on minimizing the dimensions of transistors. When the plane dimension of a gate electrode is reduced to downscale the transistor, off-current may increase due to a short channel effect (SCE) and refresh characteristics of a memory device may deteriorate. In order to prevent the performance of a MOS transistor from deteriorating due to an SCE, a recess-channel transistor having an effective channel length greater than a horizontal dimension of a gate electrode has been proposed.
An example of the recess-channel transistor has been disclosed by Min in U.S. Pat. No. 6,476,444 B1 entitled “Semiconductor Device and Method for Fabricating the Same” (hereinafter “Min”). Min can be understood to disclose wherein a gate trench is formed in an active region of a semiconductor substrate. The gate trench includes a first gate trench having a generally square section and a second gate trench connected to the first gate trench and having an elliptical section. Thereafter, a gate dielectric layer is formed using a thermal oxidation process on an inner wall of the gate trench. A gate electrode is then formed on the gate dielectric layer to fill the gate trench. Since the second gate trench has an elliptical section, a MOS transistor can include a sufficient channel region. In other words, the MOS transistor can have an increased effective channel length. However, the second gate trench has a much greater width than the first gate trench to increase the effective channel length of the MOS transistor, so that right-angled corners are formed at a boundary region between the first and second gate trenches. Generally, when a gate dielectric layer is formed by a thermal oxidation process, the gate dielectric layer is formed thinner at a right angled corner than on a plane surface of an active region. Therefore, the gate dielectric layer is formed thinner at the boundary region between the first and second gate trenches than on an inner wall of the second gate trench. Also, when the MOS transistor operates, an electric field crowding effect may occur at the boundary region between the first and second gate trenches. The effect field crowding effect leads to the generation of a gate induced drain leakage (GIDL) current. As a result, data retention characteristics of a semiconductor device such as a DRAM may deteriorate due to the GIDL current. Furthermore, it is difficult to ensure the reliability of the gate dielectric layer formed at the boundary region between the first and second gate trenches.